Scrambling-code generators and CRC generators and checkers are traditionally implemented in hardware as linear-feedback shift registers (LFSRs). However, such an implementation requires one clock cycle for every bit.
It is sometimes desirable to process the data more quickly, which can be done by taking advantage of the fact that an LFSR can be represented mathematically as a transfer matrix A, defined so that NextState=A*CurrentState (modulo 2), where NextState and CurrentState are column vectors representing the state of the LFSR. In this way, an LFSR can be emulated.
NB: The modulo 2 in the transfer function implies operations over GF(2) (i.e. everything is a bit and can only have the values 0 and 1), but this approach is certainly not limited to GF(2). However, this convention is used throughout this document since GF(2) is normally used in practical systems.
For CRC, or any LFSR whose next state and/or output depend on a data input, NextState and CurrentState have an extra element to represent the data input, in addition to the elements representing the LFSR state.
The LFSR can be made to step n times in a single clock cycle by raising A to the nth power: NextStaten=An*CurrentState (modulo 2).